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 MC74VHCT257A Quad 2-Channel Multiplexer with 3-State Outputs
The MC74VHCT257A is an advanced high speed CMOS quad 2-channel multiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It consists of four 2-input digital multiplexers with common select (S) and enable (OE) inputs. When (OE) is held High, selection of data is inhibited and all the outputs go Low. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V because it has full 5 V CMOS level output swings. The VHCT257A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage--input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems.
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16 SO-16 D SUFFIX CASE 751B VHCT257A AWLYWW 1 8 9
16
9
VHCT257A ALYW TSSOP-16 DT SUFFIX CASE 948F
1
8
* * * * * * * * * *
High Speed: tPD = 4.1 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V
16
9
EIAJ SO-16 M SUFFIX CASE 966 A L, WL Y W, WW = = = =
VHCT257A ALYW
1 8
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
Device S A0 B0 Y0 A1 B1 Y1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OE A3 B3 Y3 A2 B2 Y2 For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MC74VHCT257ADTR2 TSSOP-16 2500 Tape & Reel MC74VHCT257AM EIAJSO-16 50 Units/Rail MC74VHCT257AD MC74VHCT257ADR2 MC74VHCT257ADT Package SO-16 SO-16 TSSOP-16 Shipping 48 Units/Rail 2500 Tape & Reel 96 Units/Rail
MC74VHCT257AMEL EIAJSO-16 2000 Tape & Reel
Figure 1. Pin Assignment
(c) Semiconductor Components Industries, LLC, 2004
1
September, 2004 - Rev. 2
Publication Order Number: MC74VHCT257A/D
MC74VHCT257A
OE I0a I1a I0b I1b I0c I1c I0d I1d S
Za
Zb
Zc
Zd
Figure 2. Expanded Logic Diagram
OE S A0 B0 A1 B1 A2 B2 A3 B3
15 1 2 3 5 6 11 10 14 13
EN G1 1 1 MUX 4 7 9 12 Y0 Y1 Y2 Y3
Figure 3. IEC Logic Symbol
FUNCTION TABLE
Inputs OE H L L S X L H Outputs Y0 - Y3 Z A0 -A3 B0 -B3
A0 - A3, B0 - B3 = the levels of the respective Data-Word Inputs.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
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MC74VHCT257A
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SOIC Package TSSOP SOIC Package TSSOP Output in 3-State High or Low State Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHUP qJA
Latchup Performance
mA C/W
Thermal Resistance, Junction-to-Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1 Tested to EIA/JESD22-A114-A 2 Tested to EIA/JESD22-A115-A 3 Tested to JESD22-C101-A 4 Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 5.0 V + 0.5 V Characteristics Min 4.5 0 0 -55 0 Max 5.5 5.5 5.5 125 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Junction Temperature C 80 90 100 110 120 130 140 NORMALIZED FAILURE RATE Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110 C TJ = 130 C TJ = 100 C TJ = 120 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 4. Failure Rate vs. Time Junction Temperature
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MC74VHCT257A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Maximum High-Level Output Voltage Ou u o age VIN = VIH or VIL IOH = -50 mA VIN = VIH or VIL IOH = -8 mA VOL Maximum Low-Level Output Voltage Ou u o age VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 8 mA IIN IOZ ICCT Input Leakage Current Maximum 3-State Leakage Current Maximum Quiescent Supply Current Additional Quiescent Supply Current (per pin) Output Leakage Current VIN = 5.5 V or GND VIN = VIH or VIL VOUT = VCC or GND VIN = VCC or GND Condition (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 3.94 3.94 0 0.1 0.36 0.1 0.25 1.35 Min 2 0.8 TA = 25C Typ Max TA 85C Min 2 0.8 Max -55C TA 125C Min 2 0.8 Max Unit V V V 3.8 3.8 0.1 0.44 1.0 2.5 1.5 3.66 3.66 V 0.1 0.52 1.0 2.5 1.65 mA mA mA
ICC
VIN = VCC or GND
5.5
4.0
40
40
mA
IOPD
VOUT = 5.5 V
0
0.5
5
5
mA
II I I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I IIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII II I I I I I I I I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I IIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII II I I I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter Test Conditions TA = 25C Typ 5.8 8.3 3.6 5.1 7.0 9.5 4.0 5.5 6.7 9.2 3.6 5.1 TA = 85C 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -55C TA 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 11.0 14.5 7.0 9.0 Min Max Min Max Unit ns Maximum Propagation Delay, g y A or B to Y VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF 9.3 12.8 5.9 7.9 11.0 14.5 7.0 9.0 tPLH, tPHL Maximum Propagation Delay, g y S to Y 11.0 14.5 6.8 8.8 13.0 16.5 13.0 16.5 ns 8.0 10.0 8.0 10.0 tPZL, tPZH Maximum Output Enable, Time, Time OE to Y VCC = 3.3 0.3 V RL = 1 kW VCC = 5.0 0.5 V RL = 1 kW VCC = 3.3 0.3 V RL = 1 kW VCC = 5.0 0.5 V RL = 1 kW 10.5 14.0 6.8 11.0 12.5 16.0 12.5 16.0 ns 1.0 12.0 1.0 1.0 8.0 10.0 8.0 12.0 tPLZ, tPHZ Maximum Output Disable, Time OE to Y Time, 10.5 9.5 4 14.0 12.0 10 15.0 13.0 10 15.0 13.0 10 ns CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0 V 20 CPD Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74VHCT257A
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage OE VCC A, B or S 50% tPLH Y 50% VCC Y tPHL GND Y tPZL 50% VCC tPZH 50% VCC tPHZ tPLZ Typ 0.3 - 0.3 Max 0.8 - 0.8 2.0 0.8 VCC GND HIGH IMPEDANCE VOL + 0.3V VOH - 0.3V HIGH IMPEDANCE Unit V V V V
50%
Figure 5. Switching Waveform
Figure 6. Switching Waveform
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST
TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. Test Circuit
INPUT
Figure 9. Input Equivalent Circuit
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MC74VHCT257A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EE CCC EE
M
9
-W-
MC74VHCT257A
PACKAGE DIMENSIONS
SOIC EIAJ-16 M SUFFIX CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78
INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
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MC74VHCT257A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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MC74VHCT257A/D


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